LogicTronix Portfolio [Updated]

We have expertise on: FPGA Design, VHDL/Verilog Programming, Linux Driver Development
Featured Project’s [Completed]:
  1. Real Time Object Tracking of 2k Video with Zynq Ultrascale + MPSoC and SDSoC
  2. Video Processing with 1080p Resolution Video Stream on VIVADO, HLS and Zynq 7000.
  3. We previously Implemented the Bitcoin Mining Project on Altera and Xilinx FPGA and also did the review of XMRIG, XMR-STAK and Keccak-Miner and some other algo’s on FPGA.
  4. Customization and Implementation of Opensource Bit-coin Miner and Keccak-Miner on FPGA.
  5. AWS EC2 F1 Implementation Review and we also have take the Developer Sessions for EC2 F1 organized by Xilinx and AWS
  6. Real time Object Tracking & Recognition with FPGA, Face Recognition with PYNQ FPGA.
  7. Number Plate Recognition and Digit Recognition with FPGA on Real time Video Stream.
  8. Real time Video Processing as with Canny, Sobel etc.
  9. FPGA Design with Xilinx Tools [Xilinx VIVADO/ISE, HLS, SDSoC, PetaLinux]
    VHDL, Verilog Programming for FPGA/ASIC, Tcl Scripting, Bash Scripting, OpenCL.
    Digital signal processing with Xilinx Zynq FPGA; Design and Simulation of Digital Signal Processor on VHDL/Verilog.
  10. Implementation of Image classification Algorithm  with FPGA.
  11. Evolutionary & Meta Heuristic Algorithm implementation on FPGA for Travel Salseman Problem for getting shortest path between cities.
  12. Machine Learning with FPGA for Video and Image Processing.
Recently Completed Projects:
  • Digital Signal Processor Design on VHDL, Audio Processing with FPGA.
  • Sigma Delta ADC implementation on Xilinx Artix 7 FPGA
  • We are offering Online Course on VHDL/Verilog/MATLAB  and PCI Express Development with FPGA at Udemy
  • We previously worked for Bash Scripting for PCIe based register debugging for FPGA Devices which used lspci and setpci commands. The bash file automatically generate the BAR and other Device Register Status on text files for analysis purpose.
Our Past Project:
  • AWS EC2 F1 Implementation Review and we also have take the Developer Sessions for EC2 F1 organized by Xilinx and AWS
  • We also have created a comparison review on the best hashrate FPGA for different algo’s
  • we are also working on Custom FPGA Board Design for mining Crypto recently
  • Real time Canny Edge Detection on Video with High Level Synthesis [HLS]
  • AES encryption  & decryption IP Design on VHDL/Verilog for Xilinx and Altera FPGA
  • Back Propagation Neural Network Implementation on High Level Synthesis and FPGA
  • Face Recognition with PYNQ FPGA and Machine Learning
  • Real time Video Streaming with Xilinx Zynq FPGA with FMC Interface
Current Projects:
  • CryptoNight 7 Implementation on FPGA for Crypto-Mining.
  • Multi Object Tracking on 2k Video Stream with Zynq Ultrascale+ MPSoC.
  • Linux Driver Development for Altera FPGA with PCIe.
  • Machine Learning with FPGA for Face Recognition and Real time Video Analysis.

We have 10 different online Courses on Udemy on FPGA/VHDL/Verilog/MATLAB programming.

For any Queries and Contact Please write us at: info@logictronix.com


Acceleration of Canny Edge Detection with VIVADO HLS 

LogicTronix has design, test and implemented “Accelerated Canny Edge Detection with VIVADO HLS” on Zynq Family of FPGA. This IP can be implemented on any series of Zynq FPGA’s and other 7-series FPGA with Microblaze.

Here is the Real image and Canny edge detected image:

(Real Colored Image Source: XAPP1167, Xilinx)

Edge Detected Image by our Accelerate Canny Algorithm

Here is the complete block diagram of the canny algorithm on HLS:

Main Outlines of Canny Algorithm:

  1. Image has been taken from the FMC/HDMI source, it has been converted into AXI format
  2. AXI into MATRIX has been done, then RGBtoGRAY has been accomplished
  3. Sobel Edge calculation, Gradient Decomposition
  4. Non-Maximum Supression, Hysterisis (Edge Highlighting)
  5. MATRIX into AXI Data
  6. AXI -HDMI interconnect by FMC HDMI IP
  7. Real time Video on HDMI Display of 1080p/720p

Where Step 2-5 has been processed by Accelerated HLS IP and Step 1 and Step 6 are done by FMC HDMI IP (among which some block are available at VIVADO IP integrator)

For more details please write us at: info@logictronix.com