Monthly Archives: December 2016

15Dec/16

Internship on FPGA based Machine Learning and Neural Net Implementation

Digitronix Nepal have Some Places on AI (Machine Learning, Neural Nets) based Research & Development in FPGA. Interested enthusiast can contact us at : digitronixnepali@gmail.com or +977-9841078525.

 

Digitronix Nepal will welcome application on ML and NN and what we require is we like to engage interns on Machine Learning and Neural Nets based on FPGA Research and Development.There will be the selection process for internship.

So for the application here is Prerequisite knowledge and skills :
  1.  VHDL/Verilog and C/C++ (Basic/Moderate),
  2. Idea of FPGA (algorithm implementation on Zynq based FPGA: Zybo FPGA).
  3. AI (Neural Net and Machine Learning).
Please review also the following link (copied of google search): Neural Net implementation on FPGA
Machine Learning Implementation on FPGA
Some FAQ’s: how long this project will run and what is the procedure for selection and what number of people can attend this program.
Answers: this project will run for three month initially (and more depends on the objective/goal) based on more than 10 credit/week, selection procedure is based on the knowledge/skill on VHDL/Verilog,FPGA and AI, there will be one team (upto five members) working on this stream.
14Dec/16

FPGA Project Archives of LogicTronix

This Archive is based upon the collaboration between us and Digitronix Nepal Pvt. Ltd.

Project Accomplished:

–PCIe based Design (PCIe 3.0 IPI, PCIe DMA TRD)
–XDMA (DMA Subsystem for PCIe 3.0) Targeted Reference Design for Kintex Ultrascale      (KCU105) FPGA.
–Video Streaming and Processing with Zynq (Zybo) FPGA.
–Image Enhancement with Zynq FPGA.
–Verilog Course Design for Online Learning Site.
–AXI PCIe MIG Design Simulation and Implementation in Xilinx 7 Series and Ultrascale FPGA.
–Tcl Scripting for IPI design creation for PCIe Streamming Core for 7 series and Ultrascale Board.
–Understanding on Scatter Gather List (SGL Preparaion and Submission Block)Conducted Training’s on (for Professional and Academicians):
— Embedded System Design with Zynq FPGA and VIVADO (Xilinx Training Syllabus)
–System Level Design with Zynq and VIVADO (RTOS and FSB Design)(Xilinx Training Syllabus)

 

Training Programs:
–FPGA Design with Zybo FPGA and VIVADO
–FPGA Design with High Level Synthesis for Computer Vision

Research Outcomes (Paper, Proceedings and Articles) on:
–Very High Speed Packet Processing with FPGA and Custom Hardware (few Gbps to several Gbps)
–Packet Processing with heterogenous hardware: Herterogenous Computing
–RISC Processor Design
–Data Center based IP Design

Other Skill Sets:
–Skills on FPGA Design Flow with VIVADO (Xilinx Training Syllabus)
— Embedded System Design with Zynq FPGA and VIVADO (Xilinx Training Syllabus)
–System Level Design with Zynq and VIVADO (RTOS and FSB Design)(Xilinx Training Syllabus)
–Image Processing with Zynq FPGA.

Market Research:
–FPGA Market Review on Telecom, Medical and Automotive Market Segment.

Short  Reviews on:
–Packet Processing with OpenCL : Review
–SDN Implementation on FPGA
–SDR Implementation on FPGA.

Lab Instruction (for Universities/Colleges) on:
–Embedded System Design with FPGA, Designing Custom 8 bit Processor and Implementing FSM.
–HDL implementation on Digital Design, Digital Logic
–Computer Architecture Design with Verilog HDL.