All posts by logictronix


Collaborate with LogicTronix

We are looking for Business and Sales Partner for US and  European Market. Our main interest of collaboration is on Machine Learning & Computer Vision Systems, Embedded Product Development and FPGA Development for Custom Application as Crypto-Algorithms. If you are interested to collab with us then please write us at:


LogicTronix Portfolio [Updated]

We have expertise on: FPGA Design, VHDL/Verilog Programming, Linux Driver Development
Featured Project’s [Completed]:
  1. Real Time Object Tracking of 2k Video with Zynq Ultrascale + MPSoC and SDSoC
  2. Video Processing with 1080p Resolution Video Stream on VIVADO, HLS and Zynq 7000.
  3. We previously Implemented the Bitcoin Mining Project on Altera and Xilinx FPGA and also did the review of XMRIG, XMR-STAK and Keccak-Miner and some other algo’s on FPGA.
  4. Customization and Implementation of Opensource Bit-coin Miner and Keccak-Miner on FPGA.
  5. AWS EC2 F1 Implementation Review and we also have take the Developer Sessions for EC2 F1 organized by Xilinx and AWS
  6. Real time Object Tracking & Recognition with FPGA, Face Recognition with PYNQ FPGA.
  7. Number Plate Recognition and Digit Recognition with FPGA on Real time Video Stream.
  8. Real time Video Processing as with Canny, Sobel etc.
  9. FPGA Design with Xilinx Tools [Xilinx VIVADO/ISE, HLS, SDSoC, PetaLinux]
    VHDL, Verilog Programming for FPGA/ASIC, Tcl Scripting, Bash Scripting, OpenCL.
    Digital signal processing with Xilinx Zynq FPGA; Design and Simulation of Digital Signal Processor on VHDL/Verilog.
  10. Implementation of Image classification Algorithm  with FPGA.
  11. Evolutionary & Meta Heuristic Algorithm implementation on FPGA for Travel Salseman Problem for getting shortest path between cities.
  12. Machine Learning with FPGA for Video and Image Processing.
Recently Completed Projects:
  • Digital Signal Processor Design on VHDL, Audio Processing with FPGA.
  • Sigma Delta ADC implementation on Xilinx Artix 7 FPGA
  • We are offering Online Course on VHDL/Verilog/MATLAB  and PCI Express Development with FPGA at Udemy
  • We previously worked for Bash Scripting for PCIe based register debugging for FPGA Devices which used lspci and setpci commands. The bash file automatically generate the BAR and other Device Register Status on text files for analysis purpose.
Our Past Project:
  • AWS EC2 F1 Implementation Review and we also have take the Developer Sessions for EC2 F1 organized by Xilinx and AWS
  • We also have created a comparison review on the best hashrate FPGA for different algo’s
  • we are also working on Custom FPGA Board Design for mining Crypto recently
  • Real time Canny Edge Detection on Video with High Level Synthesis [HLS]
  • AES encryption  & decryption IP Design on VHDL/Verilog for Xilinx and Altera FPGA
  • Back Propagation Neural Network Implementation on High Level Synthesis and FPGA
  • Face Recognition with PYNQ FPGA and Machine Learning
  • Real time Video Streaming with Xilinx Zynq FPGA with FMC Interface
Current Projects:
  • CryptoNight 7 Implementation on FPGA for Crypto-Mining.
  • Multi Object Tracking on 2k Video Stream with Zynq Ultrascale+ MPSoC.
  • Linux Driver Development for Altera FPGA with PCIe.
  • Machine Learning with FPGA for Face Recognition and Real time Video Analysis.

We have 10 different online Courses on Udemy on FPGA/VHDL/Verilog/MATLAB programming.

For any Queries and Contact Please write us at:


“3rd National FPGA Design Competition 2018” Concludes

The “3rd National FPGA Design Competition 2018” has been concluded with the grand success today at Kathford Int’l College of Engineering and Management, Balkumari, Lalitpur. The competition was jointly organized by Kathford Int’l College of Engineering and Management, Digitronix Nepal Pvt. Ltd and LogicTronix.

The main objective of the competition is to promote electronic hardware design based on FPGA [An Reconfigurable Chip Technology] in Nepal. This Competition is the continuation of the “Second All Nepal FPGA Design Competition 2017” which was held on July 15, 2017 at Kathford Intl’ College of Engineering and Management and “First FPGA Design Competition 2016” held at July 2. 2016 at IOE Pulchowk Campus.

FPGA, a short form for Field Programmable Gate Array, is a programmable chips technology widely used in hardware systems such as mobile phones, cars to applications in space missions. The FPGA technology is fast becoming one of the market leaders in hardware system design around the world. The world’s top universities such as Harvard, MIT and Stanford have a very large scale research group doing their research based on FPGA.  The competition hopes to lay a foundation of FPGA research in Nepal by enhancing the FPGA application development skills and encouraging engineering students to do their projects on FPGA.

In the competition the total participant teams are 10, the winner of this contest is Arjun Neupane from Nepal Engineering College with project – “16-bit Microprocessor Design, Simulation and Implementation”, was awarded a cash prize of NRs. 15,000. The first runner-up, Ms. Shweta Chaudhary, Kala Raut and Ichchha Rauniyar from Khwopa Engineering Campus with the project traffic light design and prototype for Baneshowr Chowk, and the second runner-up, Mr. Subash Pandey from IOE Thapathali Campus with the project Vehicle Number Plate Recognition, received Rs. 7,000 and Rs. 4000 respectively. The award winners will also get an opportunity to receive training on Xilinx Zynq FPGA development board and Internship on FPGA research and development at Digitronix Nepal. The competition also get request from the international participant’s from Indian Institute of Technology (IIT)-India & some university students from USA, in the upcoming competition organizer will also include those international request for the participation on FPGA Design Competition.

An advisor of this event Mr. Deepesh Man Shakya, a Xilinx FPGA Engineer said this 3rd edition of FPGA Design Competition is a major milestone in introducing and enhancing FPGA education in Nepal and provide a platform for creating FPGA based research and development centers. Mr. Shakya said such initiatives could potentially turn into a design house providing hi-tech engineering jobs to many aspiring engineers within the country.

Dr. Madhusudan Kayastha , Principal of Kathford International College of Engineering and Management suggested to participant for preparing research papers and articles which will help then for further courier. The co-ordinator of this competition Mr. Krishna Gaihre from Digitronix Nepal & LogicTronix said that there has been a huge interest from engineering colleges and students towards FPGA Research and Development. Digitronix Nepal is currently focused on training, research and development of hardware designs based on FPGA. Digitronix Nepal also believes that within few years it will be create 10s of opportunities for Nepalese Engineering Graduates on the field of FPGA Design & VLSI Design.

The chief guest at the event Prof. Dr. Dinesh Kumar Sharma from IOE Pulchowk Campus lauded the event organizers and supporters for the effort they have put and also expressed his support in adopting FPGA in the mainstream engineering courses and help develop FPGA research environment in engineering colleges in Nepal.


Acceleration of Canny Edge Detection with VIVADO HLS 

LogicTronix/Digitronix Nepal has design, test and implemented “Accelerated Canny Edge Detection with VIVADO HLS”.

Here is the Real image and Canny edge detected image:

(Real Colored Image Source: XAPP1167, Xilinx)

Edge Detected Image by our Accelerate Canny Algorithm

Here is the complete block diagram of the canny algorithm on HLS:

Main Outlines of Canny Algorithm:

  1. Image has been taken from the FMC/HDMI source, it has been converted into AXI format
  2. AXI into MATRIX has been done, then RGBtoGRAY has been accomplished
  3. Sobel Edge calculation, Gradient Decomposition
  4. Non-Maximum Supression, Hysterisis (Edge Highlighting)
  5. MATRIX into AXI Data
  6. AXI -HDMI interconnect by FMC HDMI IP
  7. Real time Video on HDMI Display of 1080p/720p

Where Step 2-5 has been processed by Accelerated HLS IP and Step 1 and Step 6 are done by FMC HDMI IP (among which some block are available at VIVADO IP integrator)

For more details please write us at: or


Creating Custom AXI Slave Lite IP with VIVADO Tool

Are you interested on Creating the Custom IP of AXI Slave Lite with VIVADO Tool? Here we have an tutorial on youtube channel. This tutorial make you clear about the IP design methodology, Packaging Options of IP and Utilizing the IP with Other peripherals and Processing Systems.


Internship on FPGA based Machine Learning and Neural Net Implementation

Digitronix Nepal have Some Places on AI (Machine Learning, Neural Nets) based Research & Development in FPGA. Interested enthusiast can contact us at : or +977-9841078525.


Digitronix Nepal will welcome application on ML and NN and what we require is we like to engage interns on Machine Learning and Neural Nets based on FPGA Research and Development.There will be the selection process for internship.

So for the application here is Prerequisite knowledge and skills :
  1.  VHDL/Verilog and C/C++ (Basic/Moderate),
  2. Idea of FPGA (algorithm implementation on Zynq based FPGA: Zybo FPGA).
  3. AI (Neural Net and Machine Learning).
Please review also the following link (copied of google search): Neural Net implementation on FPGA
Machine Learning Implementation on FPGA
Some FAQ’s: how long this project will run and what is the procedure for selection and what number of people can attend this program.
Answers: this project will run for three month initially (and more depends on the objective/goal) based on more than 10 credit/week, selection procedure is based on the knowledge/skill on VHDL/Verilog,FPGA and AI, there will be one team (upto five members) working on this stream.

FPGA Project Archives of LogicTronix

This Archive is based upon the collaboration between us and Digitronix Nepal Pvt. Ltd.

Project Accomplished:

–PCIe based Design (PCIe 3.0 IPI, PCIe DMA TRD)
–XDMA (DMA Subsystem for PCIe 3.0) Targeted Reference Design for Kintex Ultrascale      (KCU105) FPGA.
–Video Streaming and Processing with Zynq (Zybo) FPGA.
–Image Enhancement with Zynq FPGA.
–Verilog Course Design for Online Learning Site.
–AXI PCIe MIG Design Simulation and Implementation in Xilinx 7 Series and Ultrascale FPGA.
–Tcl Scripting for IPI design creation for PCIe Streamming Core for 7 series and Ultrascale Board.
–Understanding on Scatter Gather List (SGL Preparaion and Submission Block)Conducted Training’s on (for Professional and Academicians):
— Embedded System Design with Zynq FPGA and VIVADO (Xilinx Training Syllabus)
–System Level Design with Zynq and VIVADO (RTOS and FSB Design)(Xilinx Training Syllabus)


Training Programs:
–FPGA Design with Zybo FPGA and VIVADO
–FPGA Design with High Level Synthesis for Computer Vision

Research Outcomes (Paper, Proceedings and Articles) on:
–Very High Speed Packet Processing with FPGA and Custom Hardware (few Gbps to several Gbps)
–Packet Processing with heterogenous hardware: Herterogenous Computing
–RISC Processor Design
–Data Center based IP Design

Other Skill Sets:
–Skills on FPGA Design Flow with VIVADO (Xilinx Training Syllabus)
— Embedded System Design with Zynq FPGA and VIVADO (Xilinx Training Syllabus)
–System Level Design with Zynq and VIVADO (RTOS and FSB Design)(Xilinx Training Syllabus)
–Image Processing with Zynq FPGA.

Market Research:
–FPGA Market Review on Telecom, Medical and Automotive Market Segment.

Short  Reviews on:
–Packet Processing with OpenCL : Review
–SDN Implementation on FPGA
–SDR Implementation on FPGA.

Lab Instruction (for Universities/Colleges) on:
–Embedded System Design with FPGA, Designing Custom 8 bit Processor and Implementing FSM.
–HDL implementation on Digital Design, Digital Logic
–Computer Architecture Design with Verilog HDL.