Tag Archives: Acceleration of Canny Edge

05Apr/18

Acceleration of Canny Edge Detection with VIVADO HLS 

LogicTronix has design, test and implemented “Accelerated Canny Edge Detection with VIVADO HLS” on Zynq Family of FPGA. This IP can be implemented on any series of Zynq FPGA’s and other 7-series FPGA with Microblaze.

Here is the Real image and Canny edge detected image:

(Real Colored Image Source: XAPP1167, Xilinx)

Edge Detected Image by our Accelerate Canny Algorithm

Here is the complete block diagram of the canny algorithm on HLS:

Main Outlines of Canny Algorithm:

  1. Image has been taken from the FMC/HDMI source, it has been converted into AXI format
  2. AXI into MATRIX has been done, then RGBtoGRAY has been accomplished
  3. Sobel Edge calculation, Gradient Decomposition
  4. Non-Maximum Supression, Hysterisis (Edge Highlighting)
  5. MATRIX into AXI Data
  6. AXI -HDMI interconnect by FMC HDMI IP
  7. Real time Video on HDMI Display of 1080p/720p

Where Step 2-5 has been processed by Accelerated HLS IP and Step 1 and Step 6 are done by FMC HDMI IP (among which some block are available at VIVADO IP integrator)

For more details please write us at: info@logictronix.com