Webinar Series on FPGA Design from LogicTronix
1.We have announced the Second Series on “Webinar Series on FPGA” in April 21, 2020.
This “Webinar Series-II” will have following Webinars:
1. Partial Reconfiguration with FPGA: Creating x4R crypto project with Partial Reconfiguration Model
2. Machine Learning with Xilinx- Vitis-AI and MPSoC FPGA
3. Designing Machine Learning Processor in RTL(VHDL/Verilog)+HLS
4. PCIe based Development with FPGA: Developing with UltraScale and UltraScale+ FPGA from Xilinx.
If you are interested on this Webinar Series-II, then please fill the registration form: https://forms.gle/1NAirkAspXhWWnKV8
We will send the schedule of the webinar to the registered enthusiast from email.
2. We have previously conducted following FREE “Webinar Series on FPGA-I” at Feb/March, 2019 :
1. Development of Computer Vision System and Machine Learning Applications with Xilinx Zynq FPGA and HLS/SDSoC
2. Hardware Design Debugging with Xilinx VIVADO Tool: Using ILA, VIO, Setup Debug Options on Hardware Debugging
3. Writing Complex VHDL/Verilog Design Systems: An example of AES Encryption/Decryption Design
4. Design with SDAccel, Alveo and VCU1525 Cards: Overview of tools and FPGA’s, basic application development with SDAccel for VCU 1525 and Alveo.
The webinar [on 1st topic] was LIVE on Sunday Feb 17, 2019 and 2nd topic at Feb 24, 3rd topic at March 3rd, and 4th topic at March 10th. The Recorded Links will be shared with the registered enthusiast. We take the registration for this webinar series from: https://forms.gle/oTY8kCTofjgLt1M7A
1. Recorded Session of Our First Webinar Series on “Computer Vision and Machine Learning with FPGA”: Watch Recorded Session of Feb 17, 2019
- VIVADO HLS IP Design for Computer Vision Applications
- Video pipeline design with DVI to RGB, AXI video to stream and AXI Stream to Video and RGB to DVI.
- Integration of TPG and VDMA
- SDK Programming for VDMA and TPG
- Machine Learning with revision stack, PYNQ Platform and on MPSoC
2. Recorded Session of Our Second Webinar Series on “Writing Complex VHDL/Verilog Design Systems”: Watch Recorded Session of Feb 24, 2019.
Topic of details on “Writing Complex VHDL/Verilog Design Systems: An example of writing Crypto Hash Function & AES Encryption/Decryption Design“:
- Some insights of VHDL and Verilog
- How to Structure the complex VHDL/Verilog projects
- How the Crypto hash function [Keccak] be written on VHDL/Verilog, an Overview of methodology. How to write keccak for 12Gh/s+ hash rate.
- Writing AES encryption and decryption module on VHDL/Verilog
Part of 2nd Webinar Session: How to Write 12Gh/s Keccak algorithm on VHDL targeting Xilinx VCU1525,
Watch the Video:
More Session of “Webinar Series on FPGA” are on plan, we will send you an email notification about its Date and Time, send us an request email to get notification of upcoming webinar on FPGA: email@example.com or fill this google form: https://forms.gle/1NAirkAspXhWWnKV8
For more details about the webinar, please contact at: firstname.lastname@example.org or email@example.com.