Webinar Series on FPGA Design from LogicTronix
1. LogicTronix going to have few Webinar in 2025.
Check here for more details: https://logictronix.com/webinars/webinars-on-fpga-2025/
2. Webinar Series – 2022 [Organized in collaboration with Xilinx]
- Watch Kria + Machine Learning Acceleration Webinar hosted by Xilinx at 2022 : https://pages.xilinx.com/EN-WB-2022-03-03-Logictronix_LP-Registration.html
- Watch ADAS Sensor Fusion and ML Acceleration with FPGA Webinar – Link
3. Webinar Series on FPGA – II, 2020.
“Webinar Series-II” had following Webinars:
- Partial Reconfiguration with FPGA: Creating x4R crypto project with Partial Reconfiguration Model
- Machine Learning with Xilinx- Vitis-AI and MPSoC FPGA
- Designing Machine Learning Processor in RTL(VHDL/Verilog)+HLS
- PCIe based Development with FPGA: Developing with UltraScale and UltraScale+ FPGA from Xilinx.
4. Webinar Series on FPGA-I , 2019 :
- Development of Computer Vision System and Machine Learning Applications with Xilinx Zynq FPGA and HLS/SDSoC
- Hardware Design Debugging with Xilinx VIVADO Tool: Using ILA, VIO, Setup Debug Options on Hardware Debugging
- Writing Complex VHDL/Verilog Design Systems: An example of AES Encryption/Decryption Design
- Design with SDAccel, Alveo and VCU1525 Cards: Overview of tools and FPGA’s, basic application development with SDAccel for VCU 1525 and Alveo.
4.1. Webinar on “Computer Vision and Machine Learning with FPGA” – [Recorded Session]
- Watch the Recorded Session at YouTube: Link
- Topic of details on “Computer Vision & Machine Learning with FPGA”:
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- VIVADO HLS IP Design for Computer Vision Applications
- Video pipeline design with DVI to RGB, AXI video to stream and AXI Stream to Video and RGB to DVI.
- Integration of TPG and VDMA
- SDK Programming for VDMA and TPG
- Machine Learning with revision stack, PYNQ Platform and on MPSoC
4.2. Webinar on “Writing Complex VHDL/Verilog Design Systems”- [Recorded Session from 2019]
- Watch the recorded session at YouTube – Link
- Topic of details on “Writing Complex VHDL/Verilog Design Systems: An example of writing Crypto Hash Function & AES Encryption/Decryption Design“:
- Some insights of VHDL and Verilog
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- How to Structure the complex VHDL/Verilog projects
- How the Crypto hash function [Keccak] be written on VHDL/Verilog, an Overview of methodology. How to write keccak for 12Gh/s+ hash rate.
- Writing AES encryption and decryption module on VHDL/Verilog
4.3. Webinar Session “How to Write 12Gh/s Keccak algorithm on VHDL targeting Xilinx VCU1525”
- Watch the recorded session at YouTube: Link